Programmable logic devices such as field programmable gate array (FPGAs) include a plurality of logic blocks interconnected by a switching fabric. The switching fabric in an FPGA requires a high routing density so that any given logic block can be selectively coupled to other logic blocks in the device. Thus, the samples per second (sps) that can be routed through an FPGA switching fabric is relatively low compared to some ASIC digital architectures.
For example, a microprocessor has dedicated routing that can be optimized for a given application such that its system clock can be relatively fast such as multiple GHz. But because the routing in an FPGA cannot be optimized as in an ASIC but must instead provide for a programmable high routing density, the system clock for an FPGA is typically much lower such as 250 Msps (0.25 GHz).
The routing fabric limitations impact FPGA performance in that functionalities such as digital signal processing slices may have the ability to function at significantly higher clocking rates. For example, an FPGA may included multiple digital signal processing (DSP) blocks (also referred to herein a slices). Each DSP slice includes a grouping of multipliers that are often capable of much higher clocking speeds as compared to the FPGA system clock used to move date though the switching fabric. But since the DSP slices can only receive data from the switching fabric, their resources are forced to be throttled to the FPGA system clock. If the switching fabric bottleneck could be removed, the number of necessary DSP resources such as multipliers could be reduced since the remaining multipliers would operate at their faster speed capabilities. For example, if the switching fabric is limited to 250 Msps but the DSP slices' multipliers can operate at 500 Msps, the number of utilized multipliers could be reduced one-half for a given DPS-exploiting design if the multipliers were enabled to operate at their 500 Msps capability.
Accordingly, there is a need in the art for improved programmable logic devices that enable high throughput DSP slices despite the use of a lower throughput switching fabric.